Nonvolatile semiconductor memories, such as EEPROM, EPROM and FLASH integrated circuits, have traditionally been used to store a single digital bit per memory cell. This has been done by changing the threshold voltage (conduction) characteristics of the cell by retaining a certain amount of charge on the floating gate of the memory cell. The threshold voltage range is normally partitioned into two levels (conducting versus nonconducting) to represent the storage of one digital bit per memory cell.
A wide range of charge can be reliably stored on the floating gate to represent a range of threshold voltages. Charge retention on the floating gate can be partitioned to represent multiple number of threshold voltage ranges and the threshold range can be partitioned into multiple ranges to represent storage of more than one bit of digital data per memory cell. For example, four threshold partitions can be used to represent storage of two digital bits per memory location and sixteen partitions to represent storage of four digital bits per memory location. Furthermore, the threshold voltage range can be partitioned to appropriately finer resolution to represent the direct storage of analog information per memory cell.
The ability to store multiple digital bits per memory cell increases the effective storage density per unit area and reduces the cost of storage per digital bit. In addition to this, in the field of semiconductor memories, the costs of a modern fabrication facility often exceeds a billion dollars. Application of multibit storage per cell techniques to existing memory fabrication processes and facilities allows the production of the next generation of higher density storage devices in the same manufacturing facilities, thereby increasing profitability and the return on investment.
Nonetheless, the problem of operational speed, i.e., the reading and writing operations, have yet to be satisfactorily addressed for devices having multiple bits per memory cell. A related problem is power dissipation. As more power is used to increase operational speeds, power consumption is also undesirably increased. Still another problem is reliability. While charges can be stored in the floating gates of memory cells for very long periods, erasing and rewriting charges causes long term problems as to the certainty of the bits stored in a memory cell. And, of course, any integrated circuit has problems of space. In an integrated circuit having multiple bits per cell, additional circuits must be added to handle the new requirements. This partially negates the advantages of the increased bits per memory cell.
The present invention solves or substantially mitigates these problems. The present invention speeds up the reading and writing operations of multibit memory cells. Power dissipation is lowered for reading operations. The present invention also permits the reliable determination of the bits in the memory cells over the long term and also conserves space on the integrated circuit.